A double dynamic random access memory (DRAM) cell comprising two vertically stacked access transistors and storage capacitors. A first access transistor is formed on a silicon substrate. A seed contact to the first access transistor is then utilized for growing an intermediate silicon substrate by Confined Lateral Selective Epitaxial Overgrowth (CLSEG). A second access transistor is formed upon the intermediate silicon substrate. A storage capacitor for the first access transistor may be formed as a trench capacitor in the silicon substrate. A storage capacitor for the second access transistor may be stacked on the second access transistor. A common buried bit line connects the two access transistors.
申请公布号
US5122476(A)
申请公布日期
1992.06.16
申请号
US19910703185
申请日期
1991.05.20
申请人
MICRON TECHNOLOGY, INC.
发明人
FAZAN, PIERRE C.;CHAN, HIANG C.;LIU, YAUH-CHING;SANDHU, GURTEJ S.;RHODES, HOWARD E.