| 摘要 |
A digital oscillator clocked by clock pulses (T) produces an output rectangular wave, the phase of which is controlled by a magnitude supplied to a D register (8'). The most significant bits of that magnitude are derived from the contents of a counter (4) clocked by the output signal (S), while some less significant bits of that magnitude, representing the progression of equal fractions of the period of the output wave are generated by a combination of the undelayed output wave and at least one delayed output wave which combination is stored at intervals of the reference frequency to which the oscillator is locked. That stored combination is converted from a Gray code to a binary code for compatibility with the counter state. The converted additional bits also control a multiplexer which selects the correspondingly delayed reference frequency signal for clocking a D register (15) which is loaded with the counter content and the converted additional bits. The resulting magnitude is processed in a known way to provide a suitably timed control magnitude input to the digital oscillator.
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