| 摘要 |
<p>PURPOSE:To increase the switching process speed of cells by inputting the header of a cell to be compared by (m) bits at each time from the bits of high- order digits, and comparing and deciding the current output of the input bit sequence. CONSTITUTION:The parallel comparator 6 inputs a 1st and a 2nd bit sequence sent as an (m)-bit parallel signal by (m) bits at each time from the high-order bits in order in synchronism with their synchronizing signals and outputs a comparative decision result at the point of time according to specific priority order if the 1st and 2nd bit sequences are in large/small relation. Further, an element switch 7 receives the large/small comparative decision result of the headers of the inputted cells from the parallel comparator 6 to switch those cells. Consequently, the cells can be processed at a time at a bit rate (m) times as high as that of an element switch 7 which uses a serial comparator.</p> |
