| 摘要 |
PURPOSE:To obtain a clock signal at a prescribed frequency and with an accurate phase by selecting and outputting a delay signal synchronously with an edge of a reference signal or deviated by a prescribed phase difference among plural delay signals resulting from a fixed frequency signal delayed by a prescribed time respectively. CONSTITUTION:When a fixed frequency signal SREF is inputted to the input terminal (a) of a delay line circuit section 2 in a clock signal generating circuit 10, delay signals SD11-SD1m delayed by a delay time tauXn from delay blocks DEL11-DEL1m are outputted from output terminals T11-T1m respectively. On the other hand, when a reference signal STG inputted to latch circuits LAT1- LATm goes to an H level, each of the latch circuits LAT1-LATm is triggered to store a state of the circuit 2 and the result is outputted. In this case, a delay signal from an output terminal closest to the input terminal (a) representing an L level when the signal STG rises in the circuit 2 is detected by an edge detection circuit 5 and the result is outputted as a clock signal CLK1 via a data selector circuit section 7. |
