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发明名称
WIRING PROCESSING METHOD FOR DESIGNING LAYOUT OF INTEGRATED CIRCUIT
摘要
申请公布号
JPH04165648(A)
申请公布日期
1992.06.11
申请号
JP19900293094
申请日期
1990.10.30
申请人
FUJITSU LTD
发明人
KORENAGA HIROKI
分类号
H01L21/822;H01L21/82;H01L27/04
主分类号
H01L21/822
代理机构
代理人
主权项
地址
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