| 摘要 |
<p>Variable width pulse generator comprising an assembly of logic stages which are connected in cascade. Each stage is arranged in order to receive one signal amongst a set of clock signals with different phase and corresponding to one of the bits of a binary word defining the pulse width. All stages are initially disabled by a precharge pulse occurring at the beginning of each variable pulse interval. The successive stages are activated by a clock pulse selected by the preceding stage. The very last stage provides an output corresponding to a variable width pulse.</p> |
