| 摘要 |
PURPOSE:To execute the rounding processing, as well by a single carry propagation addition and to accelerate the arithmetic processing time by inputting outputs of a multiplication array and an incrementer, respectively, and simultaneously, operating in parallel plural operable carry propagation adders. CONSTITUTION:By signals 3, 4, '1' is added to an MSB side of a value of an inputted mantissa and outputted to a multiplier 8, and multipliers 8, 9 execute multiplication Ma X Mb of the mantissa, and outputs it as a signal M (2n -1,0) of 2n bits. An adder 5 executes addition of an exponential part of Ea + Eb, a corrector 6 outputs a value of (Ea + Eb - Bi), and an incrementer 7 adds '1' to the value of the corrector 6, and outputs a value of (Ea + Eb -Bi + 1). Also, in parallel to addition by a carry propagation adder 9, an operation by rounding processing circuits 10, 12 and carry propagation adders 11, 13 is executed. A selector 17 selects a result of operation corresponding to four ways of whether a normalized shift exists or not and round-up/cut-off by rounding according to MSB value of multiplying result by rounding decoders 14, 15 and multiplying array 8. In such a way, the arithmetic time is accelerated. |
