Estimating resistance and delay in an integrated circuit structure.

摘要

In a configurable logic array chip having elements interconnectable by antifuses, an antifuse test structure is provided for estimating speed and resistance of programmed antifuses in the logic array without sacrificing any of the antifuses available for programming by the end user. Antifuses programmable by the same means as those in the logic array are selectively programmed to form a test path having characteristics representative of a path formed by a user in the logic array. A signal is propagated along this test path and time delay for propagation tested by switching the signal at a rate equal to a maximum acceptable time delay, then determining whether the signal propagates through the test path within the time before the signal switches. In a preferred embodiment, the antifuse test structure is located along edges of the configurable logic array chip and each edge of the chip tested for acceptable delay. <IMAGE>