| 摘要 |
A floating point arithmetic system including an operating processor for effecting the floating point operation, a memory device for storing data to be operated and a processing device for controlling the data transfer between the operating processor and the memory device and the operating process to be executed, wherein the processing device, memory device and operating processor are mutually connected by means of an address control bus line, and the processing device and memory device are connected to each other by means of a data bus line. In the processing device, there is generated an instruction signal which includes an address code representing an address of data to be operated and an instruction code denoting the content of operation to be executed, and the instruction signal is supplied to the memory device and operating processor via the address control bus line. In response to this instruction signal, the memory device transfers the data to be operated to the operating processor and the operating processor executes the operation for the transferred data. In this manner, the data transfer and operating process can be effected substantially simultaneously by a single access.
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