| 摘要 |
<p>PURPOSE:To enable an input vector to be easily prepared for reversing FF at least once in a controlled circuit by interrupting the supply of clock signals from a control circuit section to a controlled circuit section until the former circuit section becomes capable of giving a control signal to the latter circuit section regarding a state transition instruction after a period of several clocks. CONSTITUTION:A control circuit block 1 instructs a controlled circuit block 2 to execute a program for setting the internal circuit thereof at a certain status after a period of several clocks, upon receipt of an initialize instruction from an input terminal 4 with a condition input terminal 5 kept in a certain state. Normally, the block 2 repeatedly executes the program, until the block 1 changes the first address through the internal state transition. In an LSI test machine, separate conditions are sequentially set for the terminal 5, and an initialize instruction is given thereto. The block 1, then, stops the supply of clock signals to the block 2 during the process of the initialize instruction to the program execution instruction. As a result, the block 2 can execute the next program in the condition wherein the result of the previous program execution is still retained. According to the aforesaid construction, FF in the block 2 can be easily reversed at least once during a test.</p> |
