| 摘要 |
PURPOSE:To gain a memory cell free of software error induced by an alpha line by forming a first polysilicon electrode on a selection on a selection MIS transistor and burying a third polysilicon into a vertical hole formed on a second polysilicon buried in a contact hole of a drain diffusion layer by way of a capacity insulation film. CONSTITUTION:There is formed on a P type silicon substrate 1 a gate electrode 4 which comprises a field oxide film 2, a gate insulation film 3, and a first polysilicon, and a word line 4a. A source 5 and a drain 6 composed of an N<+> type diffusion layer are formed while an interlaminar insulation film 7 and an interlaminar insulation film 8 are formed. The polysilicon is buried into a contact hole formed on the source 5 and the drain 6 and selectively etched, thereby forming a buried electrode 9 connected with the source 5 and a first charge accumulation capacity electrode 10 connected with the drain 6. Then, a vertical hole is formed on the first capacity electrode 10 of the drain 6 and a capacity insulation film 11 is formed. After the formation of the film, polysilicon is buried and selectively etched, thereby forming a second capasity electrode 12 for elestric charge accumulation. |
