发明名称
摘要 PURPOSE:To improve the reliability of the operation and to simplify the test control circuit with error checking function, by installing the means for inhibiting the operation of the pseudo error generating means and pseudo error cause setting display means and pseudo error generating means. CONSTITUTION:The means for inhibiting the operation of the pseudo error generating means and pseudo error cause setting display means and pseudo error generating means are installed. For example, usually at the time of the operation mode, the data read out from memory 1 is inputted through the data line 8 to the ECC (error correction code) checking circuit 2 as it is and almost spontaneous errors are checked. And, at the time of the test mode, the peudo error cause setting display circuit 6 is set to ON by the pseudo error setting signal (a) from CPU, is sent to the exclusive OR gate 7 without inhibiting the signal (b) in the inhibiting circuit 13 and the error condition is forcibly generated. Next, the error is detected by the ECC checking circuit 2 and error detecting circuit 3, the ECC error cause display circuit 4 is set to ON and informed to a CPU and the pseudo error generating function is stopped.
申请公布号 JPH0434180(B2) 申请公布日期 1992.06.05
申请号 JP19830056714 申请日期 1983.03.31
申请人 FUJITSU LTD 发明人 HOSHINO TOMOHARU
分类号 H04L1/24;G06F11/08;G06F11/10;G06F11/22 主分类号 H04L1/24
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