发明名称 VARIABLE DELAY CIRCUIT
摘要 PURPOSE:To obtain a quantity of delay for a long time by the aid of simple control and to provide a miniaturized IC variable delay circuit without adjustment by using another means for a delay in the case where a frequency is changed. CONSTITUTION:A write switch 5-11 is chosen to hold an input signal in an analog memory 6-11 and to read a signal by the use of a read switch 5-21. At this time the switch performs ON and OFF control in a cycle which is determined by an oscillator 1, a counter 2 and a selector 3. Accordingly the input signal is output at a cycle delay of one clock with the aid of write and read. It is possible to make the delay variable by changing the connection. The delay circuit enables delay operation having the cycle of the clock and the delay of an integral multiple of the clock cycle and the exact quantity of the delay can be set to make possible non-regulation.
申请公布号 JPH04161878(A) 申请公布日期 1992.06.05
申请号 JP19900286998 申请日期 1990.10.26
申请人 HITACHI LTD 发明人 ISHIKAWA SHIZUO;KATAKURA KAGEYOSHI
分类号 G01N29/44;A61B8/00;A61B8/14;G01N29/22;G01N29/26;G01S7/52;G01S7/523;H04R17/00 主分类号 G01N29/44
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