| 摘要 |
PURPOSE:To implement carrier recovery and sample timing recovery independently by reading a weight coefficient from a memory storing coefficients in advance based on timing error information, calculating an FIR filter output and outputting the result externally as a demodulation data. CONSTITUTION:The circuit is provided with a quasi-synchronization detection circuit 2, an A/D converter 3, an M-power complex multiplier 4, digital filter groups 8-10, complex arithmetic circuits 16, 14, an interpolation clock generating circuit 15, a delay device 19, a complex multiplier 6, an interpolation channel filter 18 and a weight coefficient memory 17. Then the interpolation channel filter 18 receiving an output of the weight coefficient memory 17 and outputs the result as a demodulation data. Thus, the carrier recovery and sample timing recovery are implemented independently and burst operation is quickly attained. |
