| 摘要 |
The circuit includes a timing generating section (1) for generating four clock signals (S1-S4) to operate the hardware. A program counter section (2) reads out a user program, and a code latch section (3) latches the data read by the section (2), while a memory (4) stores various data. A hardware logic section (5) executes control setting and clearing commands to set or clear the master control. A hardware read/write generating section (6) reads the master control setting and clearing commands to set the relevant information bits. With the circuit, the command processing time is shortened, and the circuit can be applied to a large scale system.
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