| 摘要 |
<p>PURPOSE:To save software by permitting CPU to access common RAM so as to realize inter-CPU communication at the time of an allocated time band in one period generated based on the clock of master CPU. CONSTITUTION:A switch control circuit 5 supplies a switch signal which is changed over at the time of the time band when either an address bus or data bus from plural CPU is previously divided and exclusively allocated in one period based on the clock from mater CPU 3 among plural CPU to a switch 4. The switch 4 connects the data bus and the address bus of CPU, which are instructed by the switch signal to common RAM 6, accesses RAM 6 and realizes inter-CPU communication. Thus, speed can be improved and CPU can be connected with simple circuit constitution.</p> |
