| 摘要 |
<p>A semiconductor memory comprising a memory cell array (1), a first address bus (2) for transferring external address signals, a second address bus (3) for transferring internal address signals, an address decoder (4), and a controller (5); wherein the address decoder (4) includes a decoding section (4A) for decoding the address signal inputted to the address decoder (4) to select the predetermined word line of the memory cell array (1) and a changing section (4B) for changing the address signal to be inputted to the decoding section (4A) to the external or internal address signal by selecting either of the first and second address buses (2 and 3). Thus, it is possible to decrease the transfer time by transferring the external and internal address signals to the address decoder (4) through the first and second address buses (2 and 3) in accordance with an address activation signal before operation mode is decided and accelerate the access time of the memory cell by decreasing the decoding time.</p> |
