| 摘要 |
PURPOSE:To achieve high speed so that an output buffer which one bit memory data corresponding to an upper address of a memory cell inputs is selected as an output target by connecting an output side of each output buffer in Wired OR in X1 bit mode. CONSTITUTION:In X1 bit mode, output sides of a plurality of output buffers 5 - 8 are connected in Wired OR for forming a selector with an output buffer itself and an output buffer which an upper level address data inputs is selected. In X multiple bit mode, data is output independently from the output buffers 5 - 8. Then, no extra things are provided at the input side of the output buffer, thus preventing speed-up between an I/O sense amplifier and the output buffer. Therefore, it becomes possible to switch between X 1 bit mode and multiple bit mode configurations easily and to enable request for high speed and multiple types to be met. |
