| 摘要 |
<p>A multi-port RAM register file adapted for flowing data directly from an input port of the register file to an output port of the register file and for simultaneously writing to a memory location in the register file. In addition to the RAM register, the apparatus includes, in a first embodiment, (1) first and second sets of multiplexers, the first set of multiplexers connected between the register file output ports on the one hand, and, on the other hand, the outputs of the second set of multiplexers and the RAM bit lines; the second set of multiplexers being connected between one input of the first set of multiplexers, as aforementioned, and the RAM register file input ports; and (3) flow-through address comparators for controlling the multiplexers. The bit buses of the RAM are driven directly from the register file input ports. In a second embodiment, the first and second multiplexers are combined, with the outputs of the RAM bit lines being connected to inputs of the combined multiplexer, and with the combined multiplexer forming a crossbar switch.</p> |
