| 摘要 |
2. System of recognising digital circuit sequence status containing RAM type memories with outputs applied to the logical function circuit, connected with sequence recognition circuit operating in sync with the tested lines status recognition clock; is characterised in that status recognition circuit (6) passes sequence status to the control circuit (8) and the control circuit (8), based on status of the input line and in sync with status recognition clock (TAKT), controls logical function implementation circuit (5), memory outputs and status transfer buffer (7) between the input lines; it also generates to all RAM memories (1,2,3,4) addresses of recognised status tables.<IMAGE>
|
