| 摘要 |
PURPOSE:To make a delay resolution to a timing pulse double and to reduce the increase of cost in a timing pulse delay circuit by adding a flip-flop and an exclusive OR circuit to the timing pulse delay circuit. CONSTITUTION:The circuit is provided with a data latch circuit 1 for which timing pulse 11 and the 1st delay setting data are inputted, a flip-flop 2 for frequency-dividing a clock 12 into a half, the exclusive OR circuit 3 for which the output from the flip-flop 2 and the 2nd delay setting data are inputted, a counter 4 that sets the output from the data latch circuit 1, that is started by the timing pulse 11, and that counts the output from the exclusive OR circuit 3, and a detecting circuit 5 for detecting the output from the counter 4, and a flip-flop 6 that uses the output from the detecting circuit 5 as D input and a clock 13 as pulse input. Thus, the delay setting resolution is made double without changing the operation speed of the counter 4. |
