| 摘要 |
<p>A binary integer multiplier including a plurality of adder stages, each of such adder stages including a plurality of cells equal to a number of bits in an operand, each of such adder stage including a pair of full adders capable of receiving six input bits and producing two result bits at the significance level of the cell and two carry bits at the next higher significance level, apparatus interconnecting the bits indicating partial products to the input terminals of a cell at each significance level, apparatus interconnecting the carry output terminals of a cell to input terminals of the cell at the next significance level, apparatus interconnecting one carry output terminal of a cell to any unused input terminal at a cell of a particular stage at which only three input signals are provided, and apparatus interconnecting the result terminals of each cell to the input terminals of the cell at the same significance level at the next adder level. <IMAGE></p> |
