Forming trenches in single crystal silicon@ wafers - includes forming etching mask contg. parallelogram shaped window on (110) wafer face, anisotropically etching, etc.

摘要

Trenches in a single crystalline Si wafer with a (110) surface lane are formed using a masking layer featuring openings in the shape of a parallelogram with angles which are not 90 deg., and etched with an anisotropic process. The trench formed has at least one vertical and at least one sloping (6.1,6.2..) wall. The mask window has been aligned pref. with the long sides, which must form vertical sides, parallel to an intersection of the (110) plane with one of the 4 planes (1-11), (-11-1), (-111) or (1-1-1). The edges of the parallelogram which must form sloping walls, pref. the short sides, must be parallel to intersections of the (110) plane and the (111) or (11-1) planes. The etchant used is pref. 6-9 mole/l. of KOH at pref. 90 deg.C at which the etch rate ratio of 110 to 311 is as small as possible. The process also requires overhanging mask edges which are obtained by isotropic etching before the anisotropic etching is carried out. The parallelogram pref. has long sides which correspond with vertical walls and short sides corresp. with the sloping walls. USE/ADVANTAGE - The etching process is simple and reproducible. It produces vertical walls without excessive facets at the bottom of the trench. The etched surfaces are free of contamination and relatively few crystal defects are generated. The under cutting and trench dimensions have small tolerances. The process is used in the mfr. of GTO thyristors and/or field controlled thyristors.