| 摘要 |
PURPOSE:To use the refresh cycle time effectively, by controlling a priority level determining circuit through an inhibiting circuit in accordance with the first and the second priority terms set in one period of the refresh memory cycle. CONSTITUTION:Refresh scheduler 1 generates the refresh request at every fixed period and inverts FF22 of inhibiting circuit 26 to the high level during the second priority time of the refresh period. Simultaneously, output Q' of FF23 is inverted in the first priority time except the second priority time in one period of the refresh memory cycle through delay circuit 24, and inhibition signal INH is inverted to the high level to control NAND gates 17 and 18 of priority level determining circuit 25, AND gates 19 and 20, etc. As a result, priority is given to the access of memory 5 due to direct memory access device 2 in the first priority time, and priority is given to the refresh of memory 5 in the second priority time, and thus, the refresh cycle is used effectively to prevent lowering of the data transfer capability. |
