| 摘要 |
PURPOSE:To enhance the integration of the semiconductor memory unit by a method wherein distributed resistances in the collector layers are used as they are as the load resistances to be connected to the collectors. CONSTITUTION:Base terminals B's of transistors Q1, Q2 are led out from respective base layers, and emitter terminals E's from emitter layers. Power source terminals CP's are led out from collector layers through high resistors RH's, and Schottky junction terminals S's through low resistors RL's and Schottky junction elements DS's and output terminals CO's are respectively led out. A pair of the transistors Q1, Q2 constitute a flip-flop. Then power source terminal CP of the transistor Q1 is connected to a bit line B1, and moreover the Schottky junction terminal S is connected to a bit line B2. The power source terminal CP of the transistor Q2 is connected to the bit line B2, and the Schottky junction terminal S is connected to the bit line B1. Emitter terminals of the transistors Q1, Q2 are connected to a word line W. |
