| 摘要 |
<p>The present invention relates to a processor comprising a plurality of operating units for performing a parallel process. It comprises a plurality of registers where a plurality of registers can be specified with the same address; a plurality of selection sequence storages for storing the selection sequence of the registers; a plurality of determination identification storages for storing the determination as to whether or not the contents of the registers are determined; a register selector for specifying a register according to the contents of the selection sequence storages and for updating the contents of the selection sequence storages; and a determination identifier for rewriting the contents of the determination identification storages when the contents of the register are determined as correct as a result. <IMAGE></p> |
