| 摘要 |
PURPOSE:To increase the response speed of a computer by omitting the need to transfer the same data for plural times and the need to decide the correctness of these data, and shortening the data transfer time. CONSTITUTION:The counting capacity of a counter 19 which counts the synchronizing clocks is set larger than the number of clocks needed for transfer of data. A shift register control means 15 detects that the counter 19 counted the synchronizing clocks needed for transfer of data and inhibits the shift action of a shift register 9. While the overrun detecting means 20 and 22 detect whether or not the count value of the counter 19 is changed after the detecting action of the means 15. Then a data transfer error can be recognized based on the detecting results of both means 20 and 22. The contents of a flag 22 are decided within a prescribed period of time after the end of the transfer of data. Thus it is checked whether the noise is produced or not to the external synchronizing clock SCP. Then the correctness of data can be decided. This can omit the need to transfer data for plural times to confirm the correctness of data. |
