| 摘要 |
PURPOSE:To enable a chip to be lessened in development term and cost and offered at a low cost by a method wherein a vertically accumulated ion switching masked ROM is used when a ROM is m in capacity, and a vertically accumulated aluminum switching masked ROM is used when a ROM is m/2 in capacity. CONSTITUTION:A part where an N-channel diffusion layer 12 which serves as the channel, the source, and the drain of a MOS transistor and a polysilicon 13 which serves as the gate of a MOS transistor to which address data signals are transmitted are made to intersect each other is made to serve as an NMOS transistor. The number of NMOS transistors is m when a ROM is m in capacity, and data 0 or 1 is determined depending on that, an NMOS transistor is turned into a depression transistor by implanting phosphorus ions into an ion implantation part 14 of the NMOS transistor or into an enhancement transistor without implanting ions into the ion implanting part 14. The number of NMOS transistors is m/2 when a ROM is m/2 in capacity, and data 0 or 1 is determined depending on that the source and the drain of an NMOS transistor are short- circuited to the N-ch diffusion layer 12 with an aluminum 16 through the intermediary of a diffused aluminum contact 15. |
