| 摘要 |
PURPOSE:To simplify the circuit constitution by clamping a digital data resulting from A/D conversion of an inputted video signal to processing clamp level being 0 or over so as to eliminate the need for a coding circuit and a decoding circuit. CONSTITUTION:An inputted video signal S is inputted to a clamp circuit 1 and a clock generating circuit 3. The circuit 1 clamps the signal S to be within a dynamic range of an A/D converter circuit 2 but does not use the dynamic range fully so as to give a margin to a lower level at the bottom of a synchronizing signal. The signal S after clamping is given to the A/D converter circuit 2 by using the clock from the circuit 3, in which the signal is A/D-converted. The signal is converted into an optical signal via a parallel/serial conversion circuit 4 and the signal is sent to a transmission line 8. The receiver side receives the signal and reproduces a video signal via an O/E conversion circuit 6, a clock extraction circuit 7, a serial/parallel conversion circuit 9, a D/A converter 10. |
