发明名称 OUTPUT CIRCUIT INCLUDING INTEGRATED CIRCUIT
摘要 PURPOSE:To realize the multi-channel circuit by setting a level fed to the collector of an NPN transistor(TR) whose base is connected to the collector of a PNP TR smaller than a power supply voltage so as to reduce the power consumption in the inside of the IC. CONSTITUTION:This circuit consists of a PNP TR 101, an NPN TR 102 whose base is connected to the collector of the TR 101, a voltage source VC applying a level to the emitter of the PNP TR 101 and a voltage drop means 2 provided on the outside of an integrated circuit 1 and setting a level fed to the collector of the NPN TR 102 smaller than the level of the voltage source VC. When the PNP TR 101 is turned on, the collector current flows to a base and the NPN TR 102 is turned on. In this case, a voltage applied to the NPN TR 102 is set lower than the power supply voltage VC of the voltage dropping means 2. Thus, the power consumption in the inside of the integrated circuit 1 is reduced and the multi-channel circuit is realized.
申请公布号 JPH04150223(A) 申请公布日期 1992.05.22
申请号 JP19900273041 申请日期 1990.10.10
申请人 NIPPONDENSO CO LTD 发明人 HARADA TAKASHI
分类号 H03K17/00;H03K17/615;H03K19/00 主分类号 H03K17/00
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