发明名称 Carry propagation circuit for decimal code arithmetic circuits - has additional output logic circuitry for rapid processing of carrier
摘要 A digital arithmetic circuit provides addition and substractor of decimally coded numbers with a 5211 weighting. The input bits of the two numbers (A,B) are received by a combinational logic section (1-7) and a pair of binary full adder stages (25,26). A carry input (X) is combined and the carry (y) results from a logic gate (27) coupled to the output line (c) as part of an output adder stage (30). A flip-flop provides a latching function. ADVANTAGE - Reduces carry propagation time in parallel addition or substraction.
申请公布号 DE4036650(A1) 申请公布日期 1992.05.21
申请号 DE19904036650 申请日期 1990.11.16
申请人 MERKLE, PAUL, 7032 SINDELFINGEN, DE 发明人 MERKLE, PAUL, 7032 SINDELFINGEN, DE
分类号 G06F7/491;G06F7/50 主分类号 G06F7/491
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