Cache control unit for fault tolerant computer system

摘要

A fault tolerant computer system operates with a cache memory control unit in which there is a stack memory (25) that has a FIFO structure. The memory connects to a control module (23). Address and control lines (7,8) provide a link between a microprocessor (1), a characteristic memory (21), a comparator (22), a bus monitor (24), a cache memory (3), an interface (4) and the stack memory. The input addresses for a cache block are held in the stack memory. Information is read and is subjected to a comparison process before being written back into the memory.