发明名称 BUS LINE TEST METHOD AND DEVICE FOR EXECUTING THE METHOD
摘要 PURPOSE:To test the disconnection of individual bit and a short circuit between all bits in a short time with high reliability by making a value corresponding to the order bit of the bus line of a pattern n+1 as 1, making a (1 to m-1)th bit as 0s, and making the order of the numbering of the bit of the bus line optional. CONSTITUTION:In the pattern n+1, a setting where one is 0 data and the other is 1 to a pair of 2 bits whose bus lines are all different is included in either of the patterns 1 to n. Concerning each bit of bit numbers 1 to m-2, the pattern whose bit becomes 1 or the pattern whose bit becomes 0 are included in either of the patterns 1 to n respectively. And the pattern whose bit number 0 becomes 0 and the pattern whose bit number m-2 becomes 1 are included in either of the patterns 1 to n respectively. And in the pattern n+1, the bit number 0 becomes 1 and the bit number m-1 becomes 0. Thus, the disconnection of individual bit and the short circuit between all the bits can be tested in a short time with high reliability.
申请公布号 JPH04148258(A) 申请公布日期 1992.05.21
申请号 JP19900268438 申请日期 1990.10.08
申请人 FUJITSU LTD 发明人 TAJIRI KATSUTOSHI;TERADA NOBUYUKI
分类号 G01R31/02;G06F11/00;G06F13/00 主分类号 G01R31/02
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