发明名称 MANUFACTURE OF COMPLEMENTARY SEMICONDUCTOR DEVICE
摘要 PURPOSE:To diminish PR and implantation processes to contrive to shorten the term of manufacture and to reduce a manufacturing cost by forming a P-type well region on a semiconductor substrate by ion-implanting an N-type impurity in the whole surface to form an N-type well region and to lower the effective concentration of the P-type well region, and by adjusting the surface concentration of a desired P-type well region. CONSTITUTION:A P-well 3 is formed by the ion implantation of trivalent atom. Then, an N-well 4 is formed by the ion implantation of pentavalent atom. Further, after a thick oxide film region 5 and diffusion region are formed, trivalent atom is ion-implanted in the region of the N-well forming a P-channel type MOS transistor so that the threshold voltage of a transistor is brought to a desired value. When the ion implantation is conducted also in the region of the P-well forming an N-channel type MOS transistor other than the region constituting ROM code, the depression type region of the P-well is changed into an enhancement type to form a depression transistor 6 constituting the ROM code.
申请公布号 JPH04147673(A) 申请公布日期 1992.05.21
申请号 JP19900272777 申请日期 1990.10.11
申请人 NEC KYUSHU LTD 发明人 NAKAMURA SUNAO
分类号 H01L27/112;H01L21/8246 主分类号 H01L27/112
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