A=D converter with tapped delay lines - supplying signals in opposite sequences to SR flip=flops whose outputs feed binary encoding logic

摘要

Two signal connections (E1, E2) are made to opposite ends of two delay lines (L1, L2) from which taps are taken to "set" and "reset" inputs respectively of flip-flops (1-n). The outputs are applied to encoding logic (C) which expresses the digitised data in binary form. The inputs may be derived from a common source (Q) via voltage-controlled delay elements (V1, V2) with differential analogue input connections (X). Clocked D flip-flops may be used. USE/ADVANTAGE - For time interval digitisation with picosecond resoln. With voltage-controlled delay lines (or optical equivs.) a simple digitiser can achieve high conversion speeds.