| 摘要 |
PURPOSE:To protect outputting of erroneous data caused by noise or the like from a latch circuit by transferring the data to the latch circuit according to the AND of a signal to be outputted after counting a predetermined number of pulses and a signal to be outputted every time a predetermined pulse is issued. CONSTITUTION:Serial-in/parallel-out converter 5 consists of a clock frequency discriminating circuit 52 that counts the number of pulses to be outputted from the clock terminal of microcomputer 1, a shift register 51, and a latch circuit 54. The clock frequency discriminating circuit 52 outputs a one-pulse signal every time 8-pulse input of clock signal is issued. Further, serial data is transferred to the shift register 51 and shifted in synchronous with the clock pulse. In the latch circuit 54, when an output signal from the AND circuit 53 for which an output signal is inputted from a clock frequency discriminating circuit 52 and a latch signal from port 1 is input signal from the AND circuit becomes high, the output from shift register 51 is stored in the output from latch circuit 54. |
