| 摘要 |
PURPOSE:To realize high speed floating point addition and subtraction by installing two sets of exponent subtractors and two sets of right shifters for mantissa, respectively, executing exponent comparison and shifting of each mantissa of operand and operator at a time and selecting the output said right shifter to which appropriate shift action is applied. CONSTITUTION:The present computing element for floating point consists of exponent subtractors 9 and 10, right shifters 11 and 12, mantissa selectors 13 and 14, and a mantissa adder 15. Let exponents and mantissas of operand A and operator B be EA and EB and MA and MB, respectively. The exponent subtractor 9 executes subtraction of EB-EA, and the exponent subtractor 10 executes subtraction of EA-EB. Right shifters 11 and 12 execute right shifting of mantissas MA and MB, respectively. The mantissa selector 13, if EA is smaller than EB, selects the output of right shifter 11, and selects the output of right shifter 12 if EA is equal to or greater than EB. The maintissa selector 14, if EA is smaller than EB, selects mantissa MB, and selects mantissa MA if EA is equal to or greater than EB. Further, outputs from mantissa selectors 13 and 14 are supplied to mantissa 15. |
