| 摘要 |
<p>A circuit (30) is proposed for providing wait states using address bits not used in the device address decode. The various addressed memory and peripheral devices do not utilize the entire address space and so some address bits are not utilized. A number of the unused bits are decoded (40,42) to determine the number of wait states to be developed in the operation. The address decode based wait state determination is overridden (46) for RAM operations, but followed for ROM and peripheral operations. <IMAGE></p> |
