发明名称 SCHEDULE PREPARATION SYSTEM
摘要 <p>PURPOSE:To perform flexible and optimal scheduling depending upon various circumstances by additionally utilizing the state of a next-step use device for each processing product piece in a group of processing product pieces and determining a product allotted to the device from among the processing product pieces. CONSTITUTION:Simultaneous means 31 sequentially allots one by one a lot to a device from a group of allottable lot pieces, thereby simulating the scheduling to produce a result of simulation having a lot piece allotted to each device. A next device lot-processing capability level evaluator means 32 evaluates whether or not a device to be used in the next step, for a lot piece allotted temporarily to the device is in a condition capable of lot-processing, or what number of lot pieces the device being used in the next step has the capability of processing. Thus, the evaluator means 32 registers as the evaluated values with respect to a next device lot-processing capability level item 85. Upon completion of the evaluation on the next step lot processing capability level, the scheduling time is restored to the present scheduling time and the value of each item on an imaginary second lot information table 66 is restored to a state at the present scheduling time.</p>
申请公布号 JPH04146055(A) 申请公布日期 1992.05.20
申请号 JP19900269069 申请日期 1990.10.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MATSUMOTO SHIGERU;SAWADA AKIHIRO
分类号 B23Q41/08;B65G61/00;G05B15/02;G05B19/418;G06Q50/00;G06Q50/04 主分类号 B23Q41/08
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