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发明名称
TEST MODE SETTING CIRCUIT OF SEMICONDUCTOR DEVICE
摘要
申请公布号
JPH04147073(A)
申请公布日期
1992.05.20
申请号
JP19900271752
申请日期
1990.10.09
申请人
NEC YAMAGATA LTD
发明人
URUSHIYAMA KENICHI
分类号
G01R31/28;G01R31/3185
主分类号
G01R31/28
代理机构
代理人
主权项
地址
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