| 摘要 |
A boundary-scan-testing integrated circuit adapted to both a functional test of an entire IC chip and a parametric test for input and output buffers, connected to pads of the IC chip, in a periphery cell area of the IC chip. First memory circuits are respectively formed in an input buffer portion, an output buffer portion, and a bidirectional buffer portion, which are provided in the peripheral cell area of the IC chip. Second memory devices control ON/OFF operations of active elements, formed in the input buffer portion and the bidirectional buffer portion, for supplying a pad potential. Third memory devices control ON/OFF operations of tristate buffers of the output buffer portion and the bidirectional buffer portion. The first, second, and third memory devices are serially connected, thereby constituting a shift register controlled by a first control signal. First and second data selectors are operated by data output from the shift register, thereby controlling input and output buffers, and resistors for determining a potential of pads.
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