| 摘要 |
PURPOSE:To facilitate timing design of clock signals by contriving a scan-pass circuit in such a way that each flip-flop reads the output at the time before a second clock signal is input into the preceding flip-flop, and outputs it so as to be successively shifted. CONSTITUTION:At the time of a scan-pass test, as a clock signal 10 for the scan-pass test, a clock for operating a shift resister is input. The clock signal 10 becomes the clock signal of a flip-flop 3 via a selector 8. The output of the selector 8 enters the clock terminal C of a flip-flop 2 via a selector 7. The value that the flip-flop 3 reads is the Q output signal 15 of the flip-flop 2 at the time before the clock is input into the flip-flop 2. Since it is not necessary to simultaneously input the clock signals of respective flip-flops, even if there is a clock skew or the like, shift-register operation can be carried out, thus clock-signal design can be facilitated. |
