发明名称 |
Interlevel dielectric process |
摘要 |
A process for the fabrication of integrated circuits, wherein the interlevel dielectric material is partially etched back prior to reflow. This provides a pre-reflow profile which prevents filament problems in subsequently-patterned conductor levels, and which also avoids cracking of the interlevel dielectric during reflow.
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申请公布号 |
US5114530(A) |
申请公布日期 |
1992.05.19 |
申请号 |
US19900552369 |
申请日期 |
1990.07.16 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
RAO, KALIPATNAM V.;MITCHELL, ALLAN T.;PATERSON, JAMES L. |
分类号 |
H01L21/768 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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