发明名称 WIDE TELEVISION RECEIVER
摘要 PURPOSE:To display a stable picture with less video image fluctuation by using a video signal processing means so as to apply double speed conversion to at least a real scanning line signal and an interpolation scanning line signal to a video input signal thereby generating a double speed video signal and using a display form conversion means to convert the video signal in 2 ways of display forms. CONSTITUTION:A video signal processing circuit 102 generates a real scanning line signal and an interpolation scanning line signal from a video input signal and applies double speed conversion processing able to quasi-scanning at a speed twice that of the scanning speed of a standard television signal. The video signal at double speed outputted from the circuit 102 is subjected to display form conversion by a display form conversion memory circuit 103 and the result is displayed on a wide display device 104 whose aspect ratio is 16:9. In this case, the memory read control is implemented by using a control signal without time fluctuation such as jitter caused in a fixed frequency oscillation circuit 106 asynchronous with the video input signal. Thus, a video image with high picture quality with less video image fluctuation with respect to the video signal including much jitter or skew as a VTR signal is realized.
申请公布号 JPH04144387(A) 申请公布日期 1992.05.18
申请号 JP19900266202 申请日期 1990.10.05
申请人 HITACHI LTD 发明人 NAGATA TATSUO;HIRAHATA SHIGERU;KATSUMATA KENJI;TORIGOE SHINOBU;KONNO MITSUHISA
分类号 H04N11/20;H04N3/223;H04N5/46;H04N5/66;H04N7/01;H04N7/015 主分类号 H04N11/20
代理机构 代理人
主权项
地址