发明名称 REDUCTION PROJECTION ALIGNER
摘要 PURPOSE:To make precise positioning possible and to enhance device characteristics, by comparing residual rotation quantity after the removal of reticle rotation with the rotation quantity of the base pattern of a chip on a wafer, and making compensation so that the rotation quantity of the base pattern may coincide with the residual rotation quantity. CONSTITUTION:At first, the reticle 1 of the second-layer pattern is aligned to the reference mark 5 on a wafer stage 4, and residual rotation quantity after the removal of rotation to the reference mark 5 of the reticle 1 is measured by a reticle aligning mechanism 6 and stored in a comparison operation compensator 8. Then, a wafer aligning mechanism 7 measures the positions of Y-axis and X-axis alignment marks 11, 9' and 10', 12 formed in the peripheries of two chips 13, 14 with faces on a wafer 3, and the comparison operation compensator 8 calculates the rotation quantity of the whole two chips to the reference mark 5. When a difference is found by comparison, the wafer aligning mechanism 7 rotates the wafer stage 4 and compensates it so as to suit the reticle rotation.
申请公布号 JPH04144115(A) 申请公布日期 1992.05.18
申请号 JP19900266791 申请日期 1990.10.04
申请人 NEC CORP 发明人 YONEYAMA MASAHIRO
分类号 G03F7/20;G03F9/00;H01L21/027;H01L21/30 主分类号 G03F7/20
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