发明名称 FRAME DETECTION CIRCUIT
摘要 PURPOSE:To reduce the time up to frame synchronization establishment by allowing a counter for forward protection to count each frame consecutively during hunting. CONSTITUTION:A data comparison signal generator 6 generates a data comparison instruction signal 17 for each frame, and when a coincidence signal 18 is at a high level at that time, a 1st quinary counter 7 is counted, and a 2nd quinary counter 8 is counted independently of the coincidence signal 18 for a hunting block in which a synchronizing detection signal 4 is at a low level and counted when the coincidence signal 18 is at a low level for a synchronizing establishing block in which the synchronizing detection signal 4 is at a high level. Since the 2nd quinary counter 8 for forward protection counts each frame during hunting, a succeeding hunting is proceeded in a shorter time than that by a conventional frame detection circuit in the state of pseudo frame synchronization.
申请公布号 JPH04144330(A) 申请公布日期 1992.05.18
申请号 JP19900267851 申请日期 1990.10.04
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 MASUDA KAZUAKI
分类号 H04L7/08;H04J3/06 主分类号 H04L7/08
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