发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To ensure an interval between probes of a tester when a wafer test is executed by a method wherein, in addition to a bonding pad, a pad, for probing which is used to execute the wafer test is formed of a metal interconnection on an upper layer which is situated by another layer. CONSTITUTION:Metal interconnections 4 are formed in such a way that they connect pads 2 to pads 3 for probing use which are formed at the inside of a chip situated on an upper layer from a chip constitution and which are used to execute a wafer test. The bonding pads 2 are connected to an input, an output, a GND and a power supply of a semiconductor integrated circuit at the inside of a chip; the pads 3 for probing use are connected to them. When the pads 3 for probing and the bonding pads 3 are used jointly, an interval between the pads can be made large. Thereby, a probe for a tester can be brought into contact with all the pads 2, 3 in the same manner as in the case where all the bonding pads are probed.
申请公布号 JPH04142053(A) 申请公布日期 1992.05.15
申请号 JP19900265475 申请日期 1990.10.02
申请人 MITSUBISHI ELECTRIC CORP 发明人 NISHIMAKI HIDEKATSU
分类号 G01R31/26;H01L21/66 主分类号 G01R31/26
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