| 摘要 |
The present invention relates to an arbiter of priority between at least two requesting devices each issuing, independently, a request for access to the bus of a microprocessor system. According to the invention, the arbiter of priority includes a circuit (60, 65) in which the predetermined priorities are recorded and which conveys the individual acknowledgements (HLDA1, ..., HLDAn) to the requesters which have made a request (HOLD1, ..., HOLDn) following acknowledgement (HLDA) by the microprocessor. <IMAGE>
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