| 摘要 |
<p>The wait number deciding circuit decides the wait number to satify the access time of components of computer system operated with dual speed. The circuit includes a first D flip-flop (1) for receiving clock selection signal (CKSPD) and hold recognition cycle signal (HLDA), a second D flip-flop (2) connected to the first D flip- flop (1), a first and a second JK flip-flop (3,4) set or reset by the output signal of the second flip flop (2), a system clock selection circuit (10) for selecting the system clock according to the clock selection signal (CKSPD), a data input circuit (9) comprising pull up resistors (R) and switches (S), a multiplexer (8) for multiplexing the input signal according to system clock signal and ROM access request signal (ROMS), and a wait number generator (11) for generating wait numbers (WS0,WS1) according to the output signal of the multiplexer.</p> |
