| 摘要 |
<p>The back-bias generating circuit for preventing a latch-up of a CMOS device upon power-on comprises a shunt circuit. The shunt circuit comprises a node (20), a means (60) for supplying power voltage to the node under the control of a signal for sensing the application of power voltage, an output means (40) (59) for delaying the sensing signal to output the delayed signal, the sensing signal having a predetermined pulse width, a discharging means (70) for discharging the potential of the node into a low level under the control of the output means (40,59), a discharging means (90) for discharging a back-bias voltage into a ground level under the control of the voltage state of the node (20) and a means (80) for connecting the back-bias voltage to the node.</p> |
